In integrated circuits comprising copper lines, the lines in a metallization level and the vias connecting two metallization levels may be produced using the same process, known as a damascene process. More precisely, cavities defining both the vias and the lines of the metallization level to be produced are etched in an insulating region, the cavities produced opening onto the metallization level below. These cavities are then filled with copper, and a removal step, employing chemical-mechanical polishing, allows the excess copper and the hard masks used for the etching operation to be removed.
After the etching step defining the cavities, a cleaning operation is generally carried out using an oxygen plasma so as to remove polymer residues formed during the etching on the sidewalls of the cavities. This cleaning operation has the drawback of forming undercuts in the insulating region, at the interfaces between the insulating region and the various hard masks used. These undercuts may lead to fabrication defects during the deposition of copper in the cavities, or during the deposition of a tie layer for the copper. The tie layer for the copper is deposited for example by physical vapor deposition, which does not allow a continuous tie layer to be formed over the undercuts. The copper deposited on this tie layer may then consequently have holes where the undercuts are. These holes may lead to integrated circuits being obtained that are inoperable and therefore rejected during fabrication, to a reduced lifetime of the integrated circuit or even to a short circuit.
Apart from these problems related to the cleaning of the cavities using an oxygen plasma, faults may occur in the copper lines due to electromigration or the formation of protrusions on the surface of the lines.
In this regard it has been proposed to use a tie layer comprising doped copper to improve the ability of the copper to withstand electromigration, to improve the mechanical properties of the copper and to reduce the formation of protrusions and faults. The doped copper tie layer may contain atoms of aluminum, of manganese, of tin, magnesium, silver, titanium, indium, zirconium or molecules of molybdenum nitride, and is located on the bottom and side walls of the cavities.
This being so, the use of a doped copper layer has the drawback of increasing the resistance of the finest (i.e., narrowest) copper lines.
This increase in the resistance of the finest lines has consequences for the overall operation of the integrated circuit, possibly causing increased signal propagation delay times in these lines and a poor operation of the circuit at the desired frequencies.